Boards and Netlists

The IEEE 1149.1 standard (also known as JTAG) defines a protocol for communicating with JTAG-enabled devices and controlling their pins. This functionality and the description of the JTAG device functionality contained in the BSDL files is enough to perform basic testing, using programs such as XJAnalyser. However the next level of testing (and automating test generation) requires that the test system is given information about the connectivity of the board (populated PCB) that it is testing. This is done using Netlist files.

Netlist Files

A netlist file contains data including a list of the nets present on a PCB, along with which pins on the PCB are attached to each net. There are many different formats for this file and XJDeveloper currently supports and automatically identifies over 90 different formats.

Some netlists contain more information than this, such as Bill Of Materials (BOM) information, and in many cases XJDeveloper can also read this information.

ODB++ netlists

XJTAG's preferred netlist format is ODB++. ODB++ export is available in all the major PCB design tools. The reason for preferring it is simple: as well as netlist information, this format includes layout data for the PCB. This means that when problems are found on a PCB it is possible to show the layout view of the nets involved, making it easier for the test operator to verify the fault and its physical location.

ODB++ is not a file format - it is a directory structure containing many files. Often it is packaged into a single .zip file containing that directory structure, and XJTAG can work in either case - the user can point XJTAG to the directory or the .zip file containing the ODB++ job.

Multi-Board projects

Generally, PCB design tools export a netlist for each PCB design. If your project has multiple PCBs in it (for example a PCB with a daughter card, or a backplane with several cards in it) then you will probably have a netlist for each board in the system. XJTAG supports multi-board systems the intuitive way - on the Boards Screen in XJDeveloper you simply add each board to your project using its own netlist, and then on the Connections screen you can specify the connections between boards. This means that if you modify the design of one board you simply reconfigure that board to point to the new netlist.

An alternative way to do this would be to generate a single netlist out of all the netlists in your project, but this is more painful in the long run if you wish to modify netlists, or create tests using a cut-down set of boards, or simply because boards may duplicate net names and this causes other issues. XJTAG's automatic handling of multiple boards with individual netlists is far easier to work with.

Use of BOM data

When a netlist contains BOM data, XJTAG will use that in several ways. For example, it will try to match part numbers with devices in the XJEase library and suggest how to categorise those for which it finds a match. It will use resistor values to help make suggestions of connection and pull resistors more accurate. And it will use information about which devices are not fitted to the board to improve XJDeveloper's suggestions for categorising devices.

External Hardware

XJTAG supports operation using other non-JTAG test equipment simultaneously coordinated with the JTAG tests. This is termed External Hardware or Non-JTAG Test Equipment in XJTAG's products, and more help can be found under External Hardware.

Test fixture boards

One way of testing edge connectors when using JTAG for testing is to create another PCB (also containing JTAG devices) to connect them to as part of a test fixture - that way you can test through the edge connector from one JTAG-enabled device to another. This works well, but when faults are found, generally the user is only interested in the DUT and not in the PCB in the test fixture. Defining the fixture PCB as a 'Test fixture board' on the Boards screen means that XJTAG can be configured to adjust its reporting of Connection Test faults to the parts of nets which are on the DUT, making them easier to interpret by the test operator.

When there is no netlist...

There are occasions when a PCB has to be repaired but the original design data (including the netlist) is not available. In this case, XJAnalyser can obviously still be used because it does not depend on netlist information. But in addition to this, XJDeveloper has a mode of operating (using the Manually Create Board wizard), which can semi-automatically build up a partial netlist for the board, and the user can provide more information.

Where it is known which pins on a JTAG-enabled device are connected to pins on a testable but non-JTAG device, XJDeveloper allows the user to define these connections and then run tests using our standard XJEase library files on those devices. This means that even without netlist information it is often possible to do some basic tests or programming on a PCB. This process is much slower to set up than a normal XJTAG project would be, but in the absence of netlist information it does make at least some testing possible.