Connection Test Output

In previous steps of the tutorial, you have categorised all the devices that are connected, both directly and indirectly, to JTAG enabled devices in the circuit. You can not only run tests on those devices, but you have also maximised the test coverage achieved by the Connection Test.

In this step of the tutorial, you will see the types of fault that can be detected by the Connection Test, and the way they are reported.

Open circuit faults

An open circuit error can be created on the XJDemo board using FCJ1.

This breaks a connection between the two JTAG devices.

To find out more about the data used to diagnose this fault, expand the Error Detail:

Due to the nature of open-circuit faults there can be an element of randomness in the data read on a net with such a fault, and therefore the error details you see may not look exactly as shown above.

In the case of an open circuit error, each column of information represents a JTAG enabled pin on a net; within each of these columns the write and read values for each test step is displayed. Where there is a '-' (hyphen) in the write column it means that no data was written to that pin during that test step, i.e. it was high-impedance.

You can see in the Error Detail that in the first four steps of the Connection Test the net was being driven by pin 64 on U1 and while that pin read back the expected values, the other pin on the net, U2.B4, read back a 0. The blue highlighting of these test steps means that this data was not what was expected. In this case the data has been analysed and found to be consistent with open circuit behaviour.

In the next four steps nothing was written to either of the JTAG enabled pins on this net, though this does not mean that nothing was happening. When a net is high-impedance it is being monitored to see if it reads back the values driven to other nets in the circuit, in order to detect short circuit faults.

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Short circuit faults

You can also use FCJ1 to create a short circuit fault between JTAG enabled nets on the XJDemo board:

The Net Detail shows every pin on each of the two nets involved, and nets linked to those. In this case there are two pairs of pins (one on each net) which might be candidates to be shorted to each other:

• U1 – pins 33 and 34
• FCJ1 – pins 1 and 2

It is not always easy to see these potential error locations if the nets have a large number of pins.

However, because this project uses ODB++ data as the netlist for the board, each Connection Test error has a link to XJTAG's Layout Viewer, allowing you to visualise the information.

As shown below, the Layout Viewer is opened with both nets IO19-NetP3_19 and LED9_R highlighted.

In the image above, the tracks on the top layer of the PCB are shown in red, the tracks on the bottom layer are shown in blue, and the tracks on an internal layer are shown in purple. The Layout Viewer will automatically show all the layers that contain tracks for the selected nets. To change the default layer colours, see the Layout Viewer Help for Layers.

Where you have physical access you can check each of these parts of the board to find the short. In this case the fault is very likely to be at U1 or FCJ1 as the two nets do not come physically close to each other on the same layer at any other points (unless there was a fault in the bare PCB).

Schematic Viewer

When there are schematics linked to boards in a project, it is possible to open the schematic via the links for single devices, pins and nets.

The Schematic Viewer is launched and the first match for the link is highlighted on the page. From here, you can quickly cycle through all matches for the link using the Next and Previous buttons, and zoom in or out to get a better understanding of the part of the circuit where the fault has been detected.

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Logic Errors

Logic errors are diagnosed by exercising the Logic devices that have been categorised in the circuit. On the XJDemo board there are three devices that will be tested in this way during the Connection Test:

• U8 – a 74LVC125A tri-stateable buffer.
• U9 – a 74LVC2G02GS dual NOR gate.
• U10 – a 74LVC1G04SE inverter.

There is another Logic device on the XJDemo board (U15, a clock fan-out buffer) but that cannot be tested in the Connection Test. It will be tested using an XJEase Test Device File.

A fault involving a Logic device can be introduced to the XJDemo board using FCJ1.

Faults related to Logic devices are more complex than simple short-circuit or open-circuit faults. In this case the NOR gate U9 has two inputs: one is directly connected to the JTAG enabled MCU, U2, while the other is connected to the inverter U10 which is, in turn, connected to U2. The output from the NOR gate can then be sampled at JTAG enabled CPLD U1.

In the Error Detail you can see that there are two sections. The first part of the table (to the left) contains the JTAG pins that are on the net where the error was identified. In this case there is only one JTAG pin, on net DECODE. The second part of the table contains the pins and nets on the logic device(s) that were used as part of the test, including the pin where the error was detected.

The rows highlighted blue in Error Detail contain information indicating a problem in this logic block. By reviewing the highlighted rows and identifying the columns where written (W) and read (R) values differ, you can pinpoint the source of the fault.

Examining the first highlighted row for the error detected on net DECODE, it is only the U9.7 column where the W and R values do not match. The brackets around the W value in this column indicate that, at this point of testing, the net is expected to be driven to that value by a Logic device. The write value of the DECODE net is a logic Low but it is being read as a logic High. The U10.2 and U9.2 columns have no brackets as they are being directly driven and read from a JTAG device. The final column for net NetR40_1-nA17 has a bracketed W value as this net is driven by the inverter. It has a '-' (hyphen) for its R value as the Connection Test has no way of reading the net.

The fact that the DECODE net does read both logic High and logic Low indicates that this net is not stuck high or low, and is not open at either the JTAG device, U1, or the NOR gate, U9. This means that the problem is somewhere on the input to U9. Looking further at the values driven onto the nets A16 and A17 you can see that the problem occurs when both nets are driven low.

It is not possible to know the exact nature of the fault from the data – it is possible that there is an open circuit on the net between the JTAG device and the inverter input, or on the net between the inverter and the NOR gate. If you use the Schematic Viewer to look at the circuit you will see that the actual fault is that the net between the inverter and the NOR gate has been shorted to ground at FCJ1.

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Indirect Shorts

This category of fault occurs where there is a short circuit fault, but there is no direct access through JTAG to where it has occurred – instead, access is via series resistors. Such short circuit faults can be harder to detect, because if the nets you have direct access to were driven to opposing values, the voltage drop across the series resistors could allow each net to read back the value it drives. To detect these faults, one net must be high-impedance while the other is driven.

Indirect shorts are an important consideration in JTAG testing as there are many situations where you may have series resistors between your JTAG enabled devices and your peripheral devices. Because you only have access to the JTAG side of such resistors it is important that XJTAG allows the Connection Test to check for these faults.

This will create an indirect short between nets INDa and INDb with resistors R44 and R45, giving the short a resistance of 2 kΩ.

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Stuck-at faults

The Connection Test now will diagnose the stuck-at fault as shown below:

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Pull resistor faults

The Connection Test also checks that any net with a device defined as a pull resistor always reads the expected value when it is not driven. The write protect net for the EEPROM, EEPROM_WP, is pulled high by the 4.7 kΩ pull resistor R47. The fault creation jumpers, FCJ1, can be used to pull this net to the opposite value by linking in resistor R43.

The Connection Test now will diagnose the pull resistor fault as shown below:

If you expand the error detail you can see that whenever the net is not driven, it is reading low, which is not correct for a net that is meant to be pulled up.

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Untested faults

Although the Connection Test is an excellent tool for finding faults in your circuit, there are some types of fault that the Connection Test cannot find. For example, it is not possible for the Connection Test to detect open circuit faults on either the address bus or data bus of the SRAM because there is only one point of JTAG access on these nets. These faults can still be identified using JTAG; however, in order to do so XJDeveloper relies on functionality of the non-JTAG devices on the net.

An open circuit fault on the address bus can be simulated using FCJ1. This fault can be found by using the functionality of SRAM; this is done with a test written in a Test Device File, and will be described in the following steps of this tutorial.