File Types

XJTAG uses a variety of file types with different file extensions:

BSDL Files (*.bsd, *.bsdl, *.bsm)

These describe the JTAG behaviour of a chip. They are supplied by chip manufacturers, and are usually available to download from manufacturers' websites. Almost every part of the XJTAG system needs to use BSDL files.

Netlist Files

These describe the interconnects between devices in the circuit. The board designer will create this file. XJTAG supports a large number of netlist formats including ODB++, EDIF 2.0.0, PADS PCB, Protel and RINF. If you find that your netlist format is not recognised by our system, contact us so that we can add support for it.

XJTAG Project Files (*.xjd)

Contains all the configuration for a project in XJDeveloper or XJAnalyser.

XJPack Files (*.xjp)

These are the project files for XJRunner. The XJPack file is an archive file containing all the XJEase files, BSDL files, netlists and other necessary files to run the XJEase tests for a board. They are either exported from XJDeveloper or created manually using the XJPack utility.

BSDL Library Files (*.bsdllib)

XJAnalyser uses a BSDL library to store a list of the available BSDL files. This library can then be searched through for files which match the JTAG ID codes read out of the circuit during XJAnalyser setup.

Pin Mapping files (*.xjpm)

These describe how the XJLink should be set up to connect to your circuit - which pin is TDI, TDO, etc. They are used by almost all parts of the XJTAG system.

XJEase Files (*.xje)

These contain configuration data and XJEase code for a project. They are typically modified using XJDeveloper.

XJEase Library (*.xjeaselib)

An XJEase library is supplied by XJTAG and contains a library of XJEase files which are available for use in a project.

Logic Definition Files (*.ldd)

These contain truth tables and logic definitions used to categorise devices as logic. They are typically modified using XJDeveloper.

Passive Device Description (*.pdd)

These are used in XJEase to describe simple connections between parts of the circuit, such as series resistors or jumpers. They are typically modified using XJDeveloper.

SVF Files (*.svf)

These are a standard way of representing a simple set of JTAG commands, and are often used to program JTAG devices such as FPGAs. They are usually generated by FPGA programming tools, can be run from XJAnalyser or XJEase.

STAPL / Jam Files (*.stapl, *.jam)

These are similar to SVF files, and are an alternative standard way of programming devices such as FPGAs. They are usually generated by FPGA programming tools, can be run from XJAnalyser or XJEase.

Log Files

XJRunner can generate log files during testing. These have configurable file names and file suffixes (*.txt, *.log etc).

Formatted Log Files (*.xjlog)

XJRunner can produce formatted log files with the same output that was produced during testing, for later viewing.

Recording Files

If you request technical support, we may ask you to produce a recording of how your board reacts to the testing. This will produce a recording file.

Other files

XJEase can open, read and write to any file during testing, using the file handling functions.