Test Point Reduction Report

This report analyses the circuit for nets which have a test point on them. XJDeveloper then goes on to evaluate these test points and make suggestions as to whether they are needed, thus allowing the designer to save board space.

Use the first page of the Test Point Reduction wizard to specify the board for which test point elimination is required. Then use the second page to specify how XJDeveloper should detect test points in the circuit: these can be either one-pin components or have a certain designator (by default the designator "TP" is used).

How XJDeveloper suggests test points on nets for elimination

It is assumed by default that non-BGA pins on any device can be probed in some way, using a test fixture, flying probe or by hand, and this will mean that there is no need for a dedicated test point on the same net. Exceptions to this rule can be added as Devices which cannot be probed on the third page of the Test Point Reduction wizard. It might be impossible to probe because the device has leads which are too fine-pitched to probe accurately, or because nearby components on the board prevent access.

In the case of nets where every pin on the net is on a BGA device, a test point is not needed if the net has three or more JTAG input/output pins. If the net has two JTAG input/output pins the test point could be removed but at the cost of losing the ability to pinpoint open circuit errors. Finally, if the net has only one JTAG input/output pin the test point should not be removed.