XJAnalyser

Overview

Note that from XJAnalyser 4.3 onwards new projects use the Dynamic Chains feature and subchains are automatically created for each independent TDI/TDO pair (pairs which do not share a TMS or TCK). These subchains are scanned independently. For existing projects created prior to version 4.3 the previous behaviour is maintained, until the JTAG chain is edited.

XJAnalyser provides a graphical view of the JTAG chain present on the target hardware. It allows you to view and/or control, on a pin-by-pin basis, pin state (driven high/low as an output or held tristate as an input) and the current logic value of the pin.

XJAnalyser can either perform continuous write-read JTAG scans, giving instant feedback on signal changes, or it can iterate single scans under user control, allowing manual changes between each scan.

These abilities provide XJAnalyser with a variety of distinct functions:

• Verifying the connection of the JTAG chain
• Checking JTAG chain integrity and debugging problems
• Controlling pin states in a circuit
• Monitoring signal information from a circuit
• Programming JTAG devices using SVF or STAPL/JAM files

Detailed help

The links above provide an overview of the functionality of XJAnalyser. Detailed help on using the XJAnalyser user interface can be found in the XJAnalyser Reference section.

Information about JTAG, its concepts and limitations which apply to XJAnalyser can be found here.

There is also information available on troubleshooting XJAnalyser.