Compliance Patterns

Some JTAG-enabled devices require specific pins to be set in defined states for them to operate in a JTAG compliant mode. This is usually done by the application of external signals to these device pins (these signals may be driven from another JTAG-enabled device). These pins are known as compliance pins and the signals which are applied to them are collectively referred to as compliance patterns.

For example, many FPGAs have PROGRAM pins which, when pulled low, reset the boundary scan circuitry. Then the device will not be recognised in the JTAG chain, effectively 'breaking the chain'. When there are two JTAG devices, one controlling the other's compliance pattern, it should be checked that the default (reset) state is such that the compliance pattern is correctly set.

Often when designing a JTAG compatible device, the manufacturer creates a RESET signal (or another type of initialisation signal) to reset the device's JTAG boundary scan circuits. These pins must be kept in a specified state for the device to meet the IEEE 1149.1 standard (JTAG), and it is this type of pin that is often overlooked when designing RESET circuitry for a board.

Finding Compliance Patterns

If a JTAG device has a compliance pattern, it will be listed in the COMPLIANCE_PATTERNS section in the device's BSDL file. This section is about half-way through the file, just after the PIN_MAP section.

Example:

attribute COMPLIANCE_PATTERNS of XC4VSX35_FF668 : entity is
        "(PROG_B, PWRDWN_B) (11)";

In this case, both the PROG_B and PWRDWN_B pins must be held high for the device to work in JTAG mode.