EDIF Netlist Problems

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Problems with Protel-generated EDIF netlists

Some versions of Protel generate invalid EDIF netlists if hierarchical designs are processed. The problem is that empty cells which have not been defined are referenced in the netlist.

Solution

To overcome this, XJTAG has the option to ignore missing cells when dealing with EDIF netlists. In XJDeveloper simply set this option when importing the netlist.

In XJDeveloper, when you select an EDIF netlist, some additional EDIF Parameters will be shown in the Add Board dialog. If you have this problem with empty cells being referenced you should tick the Ignore missing cells checkbox to resolve the problem.

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Problems with OrCAD Capture-generated EDIF netlists

Some versions of OrCAD Capture generate invalid EDIF netlists if bus names which traverse ports do not use a range starting or ending with the index "0".

For example, if you use a bus named A[1..12], the generated netlist will correctly declare an array of twelve signals, but will attempt to reference some elements using an invalid array index. This will generate an error such as Port index X not found in array YYYYYY when XJEase attempts to parse the netlist.

Solution

To get around this problem, set the "Output busses as scalars" option in the OrCAD Capture "Tools/Create Netlist" dialog. This will prevent busses from being exported as arrays in the EDIF file.