TMS Reset Operation

The 1149.1 JTAG standard defines a state for JTAG-compliant devices called "Test-Logic-Reset", which allows the chip to function normally with its test logic disabled to prevent it affecting the normal operation of its system pins.

The JTAG system's state machine inside a JTAG-compliant device is specified such that no matter what state the state machine is in, holding the TMS pin high for at least 5 rising edges of the TCK signal will result in the device entering the Test-Logic-Reset state, and it will remain in that state while TMS remains high.

This mechanism gives test systems like XJTAG a way to make sure that JTAG devices are all in a known state before sending any other commands, for example at the start of testing when devices are not in a known state.