FAQs

How does the TCK frequency affect the Connection Test?

Some errors on a board, such as highly resistive faults, may only be visible at high or low TCK frequencies.

Furthermore, a BSDL file may not always specify the correct maximum frequency that the device can handle, so you may need to specify a lower TCK frequency on the Pin Mapping screen through the Advanced Configuration Options tab.

Connection Test Parameters

The behaviour of the Connection Test can be modified on the Connection Test tab in the Settings panel on the XJRunner Setup screen. These configuration options are useful for boards with the following problems:

• Ground bounce
• Nets that float near their logic threshold voltage
• Possible shorts via buffers
• Problems with 1149.6 testing
• Problems with differential signals
• Spurious faults found on unconnected input pins

Programmed Devices

When programmed or configured, some devices change the behaviour of their pins. For instance, configuring an I/O pin on an Altera Stratix chip as an open-collector means that it will stay as an open-collector in JTAG mode. If such a pin is not externally pulled up, the Connection Test will report a fault.

To compensate for this, you can:

• prevent the device from being configured while the JTAG tests are running;
• edit the chip's BSDL file to reflect the new behaviour; or
• ensure that the configured behaviour does not interfere with the Connection Test - e.g. by adding pull-up resistors to open-collector pins.

Chips with known problems in this area include Xilinx and Altera FPGAs. A more detailed explanation of the options for dealing with this can be found as an application note on the XJTAG website.

Open-drain / Open-collector pins

To function properly in normal circuit design, open-drain and open-collector pins need a pull resistor on the net. The Connection Test takes into account whether or not such a pull resistor has been defined in the project before reporting an error.

Why are Logic Devices tested in 2 phases?

The Connection Test splits logic testing into two phases in order to limit the number of test steps it has to perform. Phase 2 deals with logic gates which share enable or direction control pins, where it would take a very long time for the Connection Test to step through every possible state of the logic, whereas phase 1 deals with logic where it is reasonable for the Connection Test to check that every accessible state works correctly.

"Unexpected value on logic net" error: what do I do now?

Look at the state of all the pins on the logic gate in the test where an error is indicated. The error will have been detected because the write (W) and read (R) values for the net disagree. The first thing to determine is whether the pin with the error is an output or an input for the indicated logic state. If the pin is an input it implies a problem with that net. If the pin is an output (the value written will be in brackets to show it is the expected output by the logic gate, not driven directly from JTAG) then the error may be on the indicated net, but it may equally be on one of the inputs to that gate. XJTAG is unable to deduce further information - you will have to investigate using physical probes or other means of deduction.

In the error details, why is the pin's output value in brackets?

This means that the value is the calculated output from a logic gate, rather than the output of a JTAG device. The calculated value is expected because the inputs to the gate are controlled from JTAG. However, there may be JTAG devices on the net outputting the same value if they cannot be turned off. If there are faults on the inputs to the logic gate, or the logic gate itself is faulty, then the value in brackets may not be the actual value driven to the net.