Test Coverage Analysis Methodology

In order to calculate test coverage of a circuit, pins on that circuit need to first be classified into the following groups:

• Power
• Tested
• Untested
• Unconnected

Looking at whether a net is a power net, JTAG TAP net or investigating the accessibility of a net can help to determine which of the above groups the pins on that net belong to.

Power nets

These are the nets designated as power or ground on the Power/Ground Nets screen, along with any nets connected to them. All pins on these nets are listed as power pins on the Summary Statistics tab but no further analysis can be done on these nets.

If a power net is also considered to be functionally tested, the test coverage options allow you to choose whether these pins get shown as Power or Functionally tested in the statistics view and chart view.

JTAG TAP nets

These are all the nets that are connected to a TDI, TDO, TMS, TCK or nTRST pin on a JTAG device. Pins on these nets are classified as Tested but because these pins are in use as part of the Test Access Port, no further analysis can be done.

Accessible nets

XJTAG then considers the accessibility of the remaining nets - the capability of driving or reading the net using a JTAG device, logic gates or any external hardware setup in the project (such as an ICT machine being operated by XJTAG).

If the net is accessible, XJTAG can look at the pins on those nets to see which faults they are tested for. XJTAG uses data from the connection test, device tests and functional tests to produce the final coverage statistics for the following faults.

Type of fault

Shorts

All pins on a net will have the same coverage for shorts. For a net to be tested for shorts during the connection test, one of the following must be possible:

• the net is driven while the values of other nets in the circuit are read, or
• vice-versa: other nets in the circuit are driven while the value of this net is read.

The only accessible nets that cannot be tested by connection test to some extent for shorts are nets marked as having a constant Input value. This can either be due to a disable value on a bus in a device file or because the pin is set as a constant pin.

Stuck High/Stuck Low

Stuck-at faults are tested net-wide, so all pins on the same net have the same coverage for stuck high or stuck low faults.

For a net to be tested for being stuck high during the connection test, the net must be driven low and its value read back at the same time. Similarly, to check for stuck low errors, the net must be driven high and its value read back at the same time.

Opens

To test whether an individual pin is open during the connection test, XJTAG must be able to either:

• drive the net from the pin to be tested and read the signal on another pin on the net, or
• drive the net from another pin and read the signal on the pin to be tested.

This means, for instance, that pins on a net which can be driven but not read from a JTAG device can only be tested for opens if there is some way of verifying that a non-JTAG device on the net has successfully received the signals driven from the JTAG pins. Opens coverage is therefore often achieved using test device files rather than the connection test.

Functional coverage

Alternatively, a pin may be functionally tested during device tests or by verifying the basic operation on the board. XJTAG can be made aware of this by detailing the test coverage in the Busses tab of a device file or by including them in the functional tests tab.

Logic gates

For nets which are attached to logic devices, XJTAG analyses the circuit surrounding the logic block in order to deduce what coverage can be inferred from JTAG devices, externally-controlled hardware and Test Devices.

Inaccessible nets

The remaining nets are inaccesible nets which can't be driven or read by JTAG or external hadrware. These nets are therefore untested unless they are marked as being functionally tested in a device file or included on the functional tests tab. Functional coverage is the only type of test coverage available to inaccessible nets meaning that if any other faults are marked as being tested for, these will be ignored.

Single-pin inaccessible nets are by definition not just untested, but untestable, because the pin is not directly accessible and there is nothing connected to the pin to test it with. For this reason XJTAG does not count such a pin towards any of the test coverage totals. If any such pins exist in the circuit, the analysis will output a note saying how many pins have been excluded from the statistics.

N.B. For power, JTAG TAP and inaccessible nets, all pins on a net are assumed to have the same test coverage as the net itself.