EXTEST

In this mode, the functional core of the device is completely isolated from the external device pins, and control over all the pins is given over to JTAG.

The precise details of what control is available is specified in the BSDL file for the device, and varies from device to device. In a common scenario, each device pin has three associated bits in the boundary scan chain:

• Direction: Configures the pin as either an input or an output, during a JTAG write scan.
• Write Value: Holds the output value of the pin, if the pin is an output, during a JTAG write scan.
• Read Value: Captures the value read on the pin (which may in exceptional circumstances differ from the value output), on a JTAG read scan.

EXTEST mode places no requirements on the connection of JTAG to the internal logic; the two can be completely isolated. However, in EXTEST mode the JTAG user has no responsibility for ensuring that dangerous combinations of signals are avoided, and instead the component designer must ensure that the on-chip system logic is able to tolerate any permutation on input signals that can be applied.