Xilinx (Obsolete)
This pin mapping will be loaded if an older project contains a pin mapping defined as XILINX in previous versions of XJTAG. It cannot be set using a preset pin mapping in a new project, though it can be configured manually.
| Pin number | Connector Pin Description | XJLink2 Assignment |
|---|---|---|
| 1 | Vcc - reference supply | Input * |
| 2 | Unused | Input |
| 3 | Unused | Low |
| 4 | GND | Soft GND |
| 5 | nTRST - JTAG Reset | High |
| 6 | GND | Soft GND |
| 7 | TCK - JTAG clock | TCK |
| 8 | GND | Soft GND |
| 9 | Unknown | Input |
| 10 | GND | Hard GND |
| 11 | TDO - JTAG data out (from board) | TDO |
| 12 | GND | Soft GND |
| 13 | TDI - Test data in (to board) | TDI |
| 14 | GND | Soft GND |
| 15 | Unused | Low |
| 16 | GND | Soft GND |
| 17 | TMS - JTAG mode select | TMS |
| 18 | GND | Soft GND |
| 19 | Unused | Low |
| 20 | GND | Hard GND |
* The XJLink2 can support a reference voltage - define a custom pin mapping if you need this.
XJTAG v4.2.0