Project File Preamble
The project file preamble contains a description of the circuit implementation. The information in the preamble contains sufficient detail to facilitate the generation of the test patterns required in order to implement the connection and device tests.
The preamble is hierarchical, as shown below. The yellow sections are required for all boards:

Syntax
CIRCUIT NAME := name BOARD NAME := name FILENAME := "boardfile.xje"; END; ... CONNECTION LIST Inter-Board Connections END; JTAG CHAIN JTAG Chain Descriptions END; CONNTEST Connection Test Parameters END; TEST LIST XJRunner Test List END; FILES List of Additional Code Files END; END;
Example
The following example includes all aspects of the project preamble.
CIRCUIT NAME := "theCircuit" // The main board. The circuit includes an external board with a // StrongARM on it that has a JTAG connector, extending the JTAG chain. BOARD NAME := "mainBoard" FILENAME := "mainBoard.xje" END; // The extension board BOARD NAME := "extBoard" FILENAME := "extBoard.xje" END; CONNECTION LIST // Connect the two boards together. // N.B. con1 includes the JTAG connections. CONNECT DEVICE mainBoard.CON1 TO extBoard.CON1; END; JTAG CHAIN CONNECTOR "Top_DEVICE" TDI := CN1.14; TDO := CN1.12; MAPPING TDI := 14; TDO := 12; TMS := 18; TCK := 8; LOW := 3, 5, 7, 9, 11, 13, 15, 17, 19; GP0 := 6; GP1 := 10; POWER := ON; END; END; FREQUENCY := 1M; END; CONNTEST TEST := CONNTEST; MAX_NETS := 100; END; TEST LIST "Program Flash" IC12.ProgramFlash; END; END; FILES "AdditionalFile.xje"; END; END;
The sections of the preamble must be in the order given above, or a syntax error will be generated.
XJTAG v4.1.100