Board File

A board file describes one board that makes up a circuit. A project will contain one or more boards.

Syntax

{ COMPAT_VERSION := version ; }
Netlist File
{ IS_TEST_EQUIPMENT := [ TRUE | FALSE ] }
{ BOM Parameters }       // BOM information
{ Schematic Files }      // Schematic files
{ Power Nets }           // Power, ground and termination reference nets
{ JTAG Device List }     // JTAG components and BSDL files
{ Constant Pins List }   // Pins that must be held in a particular state (e.g. to disable a device)
{ Test Device List }     // Test components and XJEase device files
{ Logic Device List }    // Logic devices
{ Ignored Device List }  // Connected nets are driven by the Connection Test and the device is included in test coverage.
{ Unfitted List }        // Connected nets are driven by the Connection Test and are included in the test coverage, but the device is not.
{ Excluded Device List } // Connected nets are not driven by the Connection Test and are excluded from test coverage.
{ Disconnect List }      // Pins to be disconnected.
{ Create Device List }   // Pins to be disconnected.
{ Board Connects }       // Connections on a single board that are not in the netlist. (e.g. via a resistor or jumper)
{ Functional Tests }     // Used in DFT analysis
{ Unprobeable Devices }
{ Configuration }        // Configuration values for device files

COMPAT_VERSION

This integer value specifies the file format version of the file and is automatically written by XJTAG when a device file is saved. It is used when loading a device file to detect if the file is from a later version and is incompatible with the current version.

Describing Devices

The XJEase system has to know how to handle each device on the board, so each device must be put into one of the following sections:

• JTAG device: If a device is in the JTAG chain, put it in this section. You will need to tell XJEase where to find the BSDL file for the device.
• Test device: If a device is to be tested with XJEase, or needs to be disabled in a particular way, put it in this section. You will need to tell XJEase which XJEase file is used for the device.
• Logic device: If a device is a logic device, put it in this section.
• Ignored device: If a non-JTAG device will not be tested with XJEase, and will not drive any nets, put it in this section.
• Unfitted device: If a device will not be fitted on the board, put it in this section.
• Excluded device: If a device needs to be completely excluded from all testing and test coverage, put it in this section.
• Connection device: If a device merely connects two nets, put it in this section. Examples: Resistors, jumpers and extra wires on the board.

Modifying Netlists

There are a number of ways of modifying or augmenting the netlist:

• Disconnect List: Disconnect pins from their nets.
• Create Device List: Create new devices manually.
• Connection List: Adding passive devices or connecting pins or devices.

Example board file

This example is the corresponding board file to the example circuit preamble file given previously.

COMPAT_VERSION := 2;

NETLIST := "main.net";

POWER LIST
    POWER := VCC, VDDx, VDD;
    GROUND := GND, AGND, DGND;
END;

JTAG LIST
    U1 := "sa1100.bsd";
    IC1 := "xcs05.bsd";
END;

CONSTANT PINS
    IC1.2 := 1;
    IC1.23 := Z;
    U1."RAS(0)" := 0;
    U1."CAS(0)" := 0;
END;

DEVICE LIST
    // N.B. Both U1 and IC1 are connected to the flash, but
    // U1 has a shorter JTAG chain and therefore can scan faster.
    IC12 := "flash.xje" USE U1;
    SW4  := "switch.xje";
END;

IGNORE LIST
    // Indicate that XJTAG can safely ignore this device.
    IC2, R9, R10;
END;

UNFITTED LIST
    // These devices aren't fitted for this board revision.
    IC3, R11, R12, C1, C2, C3;
END;

CONNECTION LIST
    // Add a wire that is not described in the netlist.
    CONNECT IC1.3 TO IC7.4;
    R1, R3, R5 := "resistor.pdd";
    RP7, RP8, RP9 := "resPack.pdd";
END;

FUNCTIONAL TEST
    // Define a number of nets that have been tested functionally
    // to improve DFT analysis.
    "Power Supply Tests"
        FEEDBACK, POWER_NET;
    END;
END;

FILE_CONFIG
    VALUES
        IC12.PROGRAM_FLASH := 1;
        IC12.FLASH_FORMAT := "hex";
        IC12.FLASH_FILENAME := "flash.bin";
    END;
END;

Boards described in the project file

XJDeveloper always saves boards into their own files, but older projects may have the boards defined directly inside the project file. The syntax for the board definition is identical apart from the COMPAT_VERSION is omitted. The rest of the content just appears inline in the circuit file.

Example

CIRCUIT NAME := "theCircuit"
    BOARD NAME := "mainBoard"
        NETLIST := "main.net";

        POWER LIST
            POWER := VCC, VDDx, VDD;
            GROUND := GND, AGND, DGND;
        END;

        ...
    END;

    CONNECTION LIST
        // Connect the two boards together.
        // N.B. con1 includes the JTAG connections.
        CONNECT DEVICE mainBoard.CON1 TO extBoard.CON1;
    END;
...